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november 2002 1/17 ? vnq05xsp16 quad channel high side solid state relay n output current (continuous): 5a n cmos compatible inputs n multiplexed proportional load current sense n undervoltage & overvoltage shut- down n overvoltage clamp n thermal shut down n current limitation n very low stand-by power dissipation n protection against: n loss of ground & loss of v cc n reverse battery protection (**) description the vnq05xsp16 is a monolithic device designed in stmicroelectronics vipower m0-3 technology. it is intended for driving any type of multiple loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). this device has four independent channels and one multiplexed analog sense output which deliver a current proportional to the selected output current. senseenable pin allows to connect any number of vnq05xsp16 on the same current sense line. active current limitation combined with thermal shut-down and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. type r on (*) i out v cc vnq05xsp16 110m w 5a (*) 36 v absolute maximum rating (**) see application schematic at page 9 symbol parameter value unit v cc supply voltage (continuous) 41 v -v cc reverse supply voltage (continuous) -0.3 v i out output current (continuous), for each channel internally limited a i r reverse output current (continuous), for each channel -5 a i in input current (in1,in2,in3,in4,sela,selb,sensenable) +/- 10 ma v csense current sense maximum voltage -3 +15 v v i gnd ground current at t case < 25 c (continuous) -200 ma v esd electrostatic discharge (human body model: r=1.5 w ; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v p tot power dissipation at t case =25c 78 w e max maximum switching energy (l=1.72mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =7.5a) 76 mj t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature -55 to 150 c order codes package tube t&r powerso-16 ? vnq05xsp16 VNQ05XSP1613TR powerso-16 tm (*) per each channel
2/17 vnq05xsp16 block diagram logic undervoltage overvoltage overtemp. 1 overtemp. 2 input 1 gnd v cc output 1 quad i lim 1 k i out1 ot 1 input 2 input 3 input 4 analog mux overtemp. 3 overtemp. 4 cs1 cs2 cs3 cs4 current sense diag logic select a select b sense enable driver 1 cs 1 demag 1 output 2 output 3 output 4 same structure for the channels2,3,4 vds lim 1
3/17 vnq05xsp16 current and voltage conventions 1 2 3 4 5 6 7 8 9 10 11 ground input 4 c.sense sensenable n.c. input 1 input 2 input 3 sela selb v cc n.c. output 1 output 2 output 3 output 4 v cc 12 13 14 15 16 17 output3 input2 i out3 v out4 output2 i out2 v out3 input1 i in1 output1 i out1 output4 i out4 v out2 v out1 i in2 i in4 input3 input4 v in4 v in3 i in3 v in2 v in1 connection diagram (top view) v cc i s v cc i gnd gnd v sense i sense sense sela selb sensenable v sensenable v selb v sela i sela i selb i sensenable
4/17 vnq05xsp16 thermal data (*) when mounted on fr4 printed circuit board with 0.5 cm2 of copper area (at least 35 m m thick) connected to all v cc pins electrical characteristics (8v 5/17 vnq05xsp16 current sense (9v< v cc <16v) logic characteristics (inputs, sela&b, sensenable) note 2: current sense signal delay after positive input slope. note: sense pin doesnt have to be left floating. symbol parameter test conditions min typ max unit k 1 i out /i sense i out1 , 2 =0.1a; v sense =0.5v t j =-40...+150c 800 1000 1200 dk 1 /k 1 current sense ratio drift i out =0.1a; v sense =0.5v; t j = -40c...+150c -10 +10 % k 2 i out /i sense i out1 , 2 =1.0a, v sense =4v t j =-40...+150c 800 1000 1200 dk 2 /k 2 current sense ratio drift i out =1.0a; v sense =4v; t j =-40c...+150c -8 +8 % k 3 i out /i sense i out1 , 2 =2.0a, v sense =4v t j =-40...+150c 850 1000 1150 dk 3 /k 3 current sense ratio drift i out =2.0a; v sense =4v; t j =-40c...+150c -6 +6 % i senseo analog sense leakage current v cc =6...16v; i out =0a;v sense =0v; t j =-40c...+150c 010 m a v sense1,2,3,4 max analog sense output voltage v cc =5.5v, i out1,2,3,4 =1.0a r sense =10k w v cc >8v, i out1,2,3,4 =2.0a r sense =10k w 2 4 v v v senseh analog sense output voltage in overtemperature condition v cc =13v; r sense = 3.9k w 5.5 v r vsenseh analog sense output impedance in overtemperature condition v cc =13v; tj>t tsd ; all channels open 400 w t dsense current sense delay v cc =13v; r sense =3.9k w (see note 2) 300 500 m s symbol parameter test conditions min typ max unit v il input low level voltage 1.25 v v ih input high level voltage 3.25 v v i(hyst) input hysteresis voltage 0.5 v i il low level input current v in =1.25v 1 m a i in high level input current v in =3.25v 10 m a v icl input clamp voltage i in =1ma i in =-1ma 66.8 -0.7 8v v 2
6/17 vnq05xsp16 truth table truth table figure 1: i out /i sense versus i out conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 sensenable selb sela sense l x x high impedance hl li sense =i out1 /k hl hi sense =i out2 /k hh li sense =i out3 /k hh hi sense =i out4 /k 500 600 700 800 900 1000 1100 1200 1300 1400 1500 012345678910 i out (a) i out /i sense max. tj=-40c<<150c min. tj=-40c<<150 c typical value 1
7/17 vnq05xsp16 electrical transient requirements figure 2: switching characteristics (resistive load r l =1.3 w ) iso t/r 7637/1 test pulse test levels i test levels ii test levels iii test levels iv test levels delays and impedance 1 -25v -50v -75v -100v 2ms, 10 w 2 +25v +50v +75v +100v 0.2ms, 10 w 3a -25v -50v -100v -150v 0.1 m s, 50 w 3b +25v +50v +75v +100v 0.1 m s, 50 w 4 -4v -5v -6v -7v 10ms, 0.01 w 5 +26.5v +46.5v +66.5v +86.5v 400ms, 2 w iso t/r 7637/1 test pulse test levels result i test levels result ii test levels result iii test levels result iv 1 cc cc 2 cc cc 3a cc cc 3b cc cc 4 cc cc 5 ce ee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 1 v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
8/17 vnq05xsp16 1 figure 3: waveforms sense 1 input 1 normal operation (for example: channel1 is on) undervoltage v cc v usd v usdhyst input 1 overvoltage v cc sense 1 input 1 sense 1 load current 1 load current 1 load current 1 overtemperature input 1 sense 1 t tsd t r t j load current 1 v ov v cc > v ov v cc < v ov short to ground input 1 load current 1 sense 1 load voltage 1 input 1 load voltage 1 sense 1 load current 1 9/17 vnq05xsp16 application schematic v cc output2 c. sense d ld +5v r prot output1 r sense input1 input2 m c r prot r prot r prot input3 input4 d gnd r gnd v gnd gnd output3 r prot r prot r prot r prot output4 notes: input1,2,3,4, sela, selb, sensenable have the same structure. sela sesb sensenable gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (-v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w ) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( @ 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. a/d c par r sense x c par <10 m s c filter 1
10/17 vnq05xsp16 high level input current input clamp voltage off state output current overvoltage shutdown -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 il(off) (a) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc ( o c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc ( oc) 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (oc) 30 32.5 35 37.5 40 42.5 45 47.5 50 vov (v) input high level i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (oc) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 2.5 5 7.5 10 12.5 15 17.5 20 ilim (a) vcc=13v 1
11/17 vnq05xsp16 turn-on voltage slope turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(on) (v/ms) vcc=13v rl=2.6ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 450 500 550 600 dvout/dt(off) (v/ms) vcc=13v rl=2.6ohm on state resistance vs t case on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc ( o c) 0 25 50 75 100 125 150 175 200 225 250 ron (mohm) iout=1a vcc=8v & 36v 5 10152025303540 vcc (v) 0 25 50 75 100 125 150 175 200 ron (mohm) iout=1a tc=150oc tc= 25o c tc=-40oc 1
12/17 vnq05xsp16 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 l(mh) i lmax (a) a b c 1
13/17 vnq05xsp16 powerso-16 ? pc board r thj-amb vs pcb copper area in open box free air condition powerso-16 ? thermal data layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 6cm 2 ). 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2) rthj_amb (c/w) tj-tamb=50c 1
14/17 vnq05xsp16 thermal fitting model of a quad hsd in powerso-16 pulse calculation formula thermal parameter area/island (cm 2 ) footprint 6 r1 (c/w) 0.18 r2 (c/w) 0.8 r3 ( c/w) 0.7 r4 (c/w) 0.8 r5 (c/w) 13 r6 (c/w) 37 22 c1 (w.s/c) 0.0006 c2 (w.s/c) 1.50e-03 c3 (w.s/c) 1.75e-02 c4 (w.s/c) 0.4 c5 (w.s/c) 0.75 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t = thermal impedance junction ambient single pulse 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r14 c13 c1 4 r13 tj_1 tj_2 t_amb pd3 c7 r10 c9 c10 r9 r7 r12 r11 r8 c1 1 c1 2 c8 pd4 r16 c15 c16 r15 tj_3 tj_4 r17 r18 footprint 6 cm 2 1
15/17 vnq05xsp16 dim. mm. min. typ max. a100.051 a2 3.4 3.5 3.6 a3 1.2 1.3 1.4 a4 0.15 0.2 0.25 a0.2 b 0.27 0.35 0.43 c 0.23 0.27 0.32 d 9.4 9.5 9.6 d1 7.4 7.5 7.6 d 0 0.05 0.1 e (1) 13.85 14.1 14.35 e1 9.3 9.4 9.5 e2 7.3 7.4 7.5 e3 5.9 6.1 6.3 e0.8 e1 5.6 f0.5 g1.2 l 0.8 1 1.1 r1 0.25 r2 0.8 t 2 5 8 t1 6 (typ.) t2 10 (typ.) package weight (typ.) p013q powerso-16 tm mechanical data 1
16/17 vnq05xsp16 powerso-16 ? suggested pad layout tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b 7.4 +/- 0.1 10.5 +/- 0.1 2 +/- 0.1 0.5 +/- 0.1 0 .8 +/- 0.1 10 +/- 0.1 1
17/17 vnq05xsp16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 1

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